This invention relates in general to fabrication of integrated circuits and, more particularly, to control of an implant profile in the channel region of a field effect transistor.
When fabricating an integrated circuit which includes a field effect transistor, it is common to introduce at least one implant into the channel region between the source and drain regions, where each such implant involves doping of the semiconductor substrate in the channel region. The doping level in the channel region is much lighter than the doping levels in the source and drain regions.
It is often advantageous or desirable to have an implant profile in the channel which is not constant, but instead varies from the source to the drain. For example, it may vary in terms of the level of doping, and/or the depth of the doping. Examples of pre-existing approaches to profiling include diffusing material into the channel from the sides, or carrying out an angled implant from each side of a gate structure. While these known techniques have been generally adequate for their intended purposes, they have not been satisfactory in all respects.
The length of the channel itself is often so short that it approaches the limits of existing lithographic capabilities, and close alignment tolerances are thus needed for the various lithographic steps used to form the major elements of the transistor, such as the source, drain, gate and channel. Where the channel length itself approaches the limits of lithographic processes, achieving variation of an implant profile within the channel essentially involves sublithographic considerations that have been problematic.
For similar reasons, it has also been problematic to fabricate gate structures which have lengths that are sublithographic. Further, it has been a problem to fabricate gate lengths which approach sublithographic dimensions, and which do not require close alignment considerations for lithographic steps which are involved.
From the foregoing, it may be appreciated that a need has arisen for a method of fabricating an integrated circuit, which allows accurate control of the fabrication of certain structural features, such as accurate control of implant profiling or gate length in a field effect transistor at a sublithographic level, without a need for close alignment tolerances for lithographic steps. According to the present invention, a method is provided to address this need, and involves: providing a substrate having an upwardly facing first surface; forming on the first surface a part which has thereon a second surface that faces sidewardly; successively forming a plurality of sidewalls, including a first sidewall on the second surface and a second sidewall on the first sidewall; removing the sidewalls; and introducing an implant into the substrate, wherein a subset of the sidewalls is present when the implant is introduced into the substrate. The subset may contain no sidewalls, one sidewall, or at least two sidewalls at the time of the implant. According to another form of the present invention, a plurality of successive implants are introduced into the substrate, wherein a respective different subset of the sidewalls is present when each implant is introduced into the substrate.